1. Field of the Invention
The present invention generally relates to integrated circuits and methods for forming integrated circuits, and, more particularly, to integrated circuits having protruding source and drain regions and methods for forming integrated circuits.
2. Description of the Related Art
Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FinFET is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three-dimensional transistor which has a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET, the transistor channel is formed along the vertical sidewalls of the fin, which is also frequently referred to as a double gate transistor, or along the vertical sidewall surfaces and the upper horizontal surface of the fin, leading to a so-called tri-gate transistor. Double gate transistors and tri-gate transistors have a wide channel, and hence high performance, which can be achieved without substantially increasing the area of the substrate surface required by said transistors.
As opposed to planar MOS transistors, which are well known in the art and so their features need not be explained, FinFETs are less well known, so that the following brief explanations with regard to FIGS. 1a and 1b are provided to identify their features.
FIG. 1a illustrates, in a cut-away perspective view, a portion of a FinFET integrated circuit (IC) 100a. The illustrated portion of IC 100a includes two fins 102a and 104a that are formed from and extend upwardly from a bulk semiconductor substrate 106a. A gate electrode 108a overlies the two fins 102a and 104a and is electrically insulated from the fins 102a, 104a by a gate insulator (not illustrated). End 110a of fin 102a is appropriately impurity doped to form the source of a field effect transistor 112a, and end 114a of that fin is appropriately impurity doped to form the drain of the FET. Similarly, ends 116a and 118a of fin 104a form the source and drain, respectively, of another FET 120a. The illustrated portion of IC 100a thus includes two FinFETs 112a and 120a having a common gate electrode. In another configuration, if source 110a and 116a are electrically coupled together and drain 114a and 118a are electrically coupled together, the structure would be a two-fin FinFET having twice the gate width of either FET 112a or 120a. Oxide layer 122a forms electrical isolation between fins and between adjacent devices as is needed for the circuit being implemented. The channel of FinFET 112a extends along the sidewall 124a of fin 102a beneath gate electrode 108a, along the top 125a of the fin, as well as along the opposite sidewall not visible in this perspective view. The advantage of the FinFET structure is that, although the fin has only the narrow width represented by the arrows 126a, the channel has a width represented by at least twice the height of the fin above oxide 122a. The channel width thus can be much greater than the fin width.
As it becomes clear from the explanations regarding a FinFET configuration as shown by FIG. 1a, the source and drain regions are formed within individual fins. A common gate electrode overlies one or more fins defining the channel region of respective fins, while a continuous isolation layer is provided in the transistor pitch embedding the fin except the portion of the fin over which the gate electrode is formed. An according FinFET configuration may be manufactured in accordance with unpublished methods for fabricating integrated circuits. However, there is still another possible configuration for FinFETs which will be explained with reference to FIG. 1b. 
FIG. 1b schematically illustrates a perspective view of a FinFET integrated circuit (IC) 100b corresponding to a three-dimensional transistor configuration or tri-gate transistor configuration. As illustrated, corresponding semiconductor fins 110b may be provided in an active region 101b in combination with a dielectric material 106b. Herein, an effective fin height is adjusted by the amount or height of the dielectric material 106b filled in between the semiconductor fins 110b. The opening 120b may be provided within the gate electrode structure which is substantially represented by the spacer structure 122b, possibly in combination with a gate dielectric material, which may be formed on any exposed surface areas of the active region 101b and the semiconductor fins 110b. The opening 120b is depicted in FIG. 1b instead of a gate electrode material in order to allow for a clear perspective illustration of IC 100b and it is understood that opening 120b is filled with appropriate gate electrode material to form a gate electrode overlying fins 110b. It is understood that the dielectric material 106b may be any appropriate dielectric material, such as a high-k dielectric material and the like. Source regions 110bS and drain regions 110bD are formed in the active region 101b at respective ends of fins 110b. However, the source regions 110bS and the drain regions 110bD are not constituted by the fins 110b, i.e., are not formed in the fins 110b. A contact layer 140b which is shown in FIG. 1b has a stress-inducing layer 141b for enhancing mobility properties of charge carriers within the channel regions and another dielectric layer 142b is formed over the stress-inducing layer 141b. The IC 100b is manufactured by etching a gate recess into an active region of a semiconductor substrate and by forming fins within the gate recess by means of an appropriate mask or hard mask. In filling the gate recess with a gate electrode material, the gate electrode is formed in the gate recess over the fins. An according manufacturing method is disclosed in US patent application publication 2011/0291196.
FinFET configurations as depicted in FIG. 1b show various drawbacks which degrade device performance of semiconductor devices having said FinFETs. As is obvious from FIG. 1b, when a gate electrode is formed within recess 120b, severe parasitic capacitances will form between the gate electrode and the source regions 110bS and drain regions 110bD resulting in significantly high gate capacitances. The reason is that portions of the gate electrode disposed over sidewall surfaces of the fins cover portions of surfaces of the drain and source regions which face the gate electrode. Accordingly, these surfaces of source/drain and of the gate electrode form capacitors having undesirable high capacitances resulting in too high parasitic capacitances. FIG. 1c shows a diagram depicting graphical representations of relations between capacitance normalized to effective gate width (C measured in fF/μm, ordinate axis) plotted against gate bias (voltage applied to gate electrode measured in Volt (V), abscissa) for a FinFET according to a configuration as displayed in FIG. 1a, a FinFET according to a configuration as depicted in FIG. 1b and a conventional planar FET configuration. Reference numeral 110c denotes a curve representing behavior of a FinFET which is displayed in FIG. 1b. Reference numeral 120c denotes a curve representing behavior of a planar FET configuration and reference numeral 130c denotes a curve representing behavior of a FinFET configuration as explained with regard to FIG. 1a. FIG. 1c clearly shows that a capacitance of a FinFET according to a configuration in which the fin is formed in a gate recess (as depicted in FIG. 1b) is considerably higher than the capacitance of a planar FET. Even if the planar FET and the FinFET have similar effective gate widths, the capacitance of the FinFET is approximately twice as much as the capacitance of the planar FET. The reason is due to considerable parasitic capacitances formed between the gate electrode and source/drain regions, which are avoided in planar FET configurations. Although FinFET configurations as depicted in FIG. 1a suppress formation of parasitic capacitances between the gate electrode and source/drain regions formed within fins at their respective ends, the capacitance of according FinFETs is still higher than that of planar FETs (compare curve 130c versus curve 120c). In comparison to FinFETs as depicted in FIG. 1b, FinFETs as shown in FIG. 1a have lower parasitic capacitances between the gate electrode and source/drain regions as these are not disposed to directly face each other. Despite their advantageous characteristics with regard to aforementioned parasitic capacities, FinFETs as depicted in FIG. 1a show an increased resistance in comparison with FinFETs as depicted with regard to FIG. 1b. 
In FIG. 1d, a diagram is shown in which a resistance (resistance RON normalized to effective gate width measured in Ωμm, ordinate axis) is plotted against the gate length (LGATE measured in nm, abscissa) for a FinFET as depicted in FIG. 1a which is denoted by 110d and a FinFET as depicted in FIG. 1b which is denoted by 120d. FIG. 1d suggests that a resistance of a FinFET as depicted in FIG. 1a having source and drain regions formed within a fin is higher than that of a FinFET as depicted in FIG. 1b having source and drain regions formed adjacent to fins. The reason is that source and drain regions formed within a fin are limited by the fin width and show degraded resistance properties due to their smaller sizes. When taking the electrostatic behavior into consideration, a FinFET as depicted in FIG. 1a results in poor device performance as compared to a FinFET as shown in FIG. 1b. 
FIG. 1e shows a diagram of a universal curve obtained by plotting a normalized electric drain current during an off state (ID,OFF normalized to the effective gate width and measured in nA/μm, ordinate axis) against a normalized electrical drain saturation current during operation (ID,Sat normalized to the effective gate width and measured in μA/μm, abscissa) for a FinFET as depicted in FIG. 1a which is denoted by 110e and a FinFET as depicted in FIG. 1b which is denoted by 120e. It is shown that at the same ID,Sat the normalized electric drain current during an off state for FinFETs as depicted in FIG. 1a is substantially higher than the normalized electric drain current during an off state for FinFETs as depicted in FIG. 1b. Usually, drive currents (ID,Sat) are compared at same ID,off.
FIGS. 1c-1e illustrate that a FinFET according to a configuration as depicted in FIG. 1a shows a lower capacitance in comparison with a FinFET according to a configuration as depicted in FIG. 1b, though the electrostatic behavior and the resistance of a FinFET according to FIG. 1a is disadvantageous as compared to a FinFET according to a configuration as depicted in FIG. 1b. 
U.S. Pat. No. 6,812,075 B2 shows a vertically oriented FET having a self-aligned dog-bone structure, wherein each of the source and drain regions have tapered portions abutting the channel region. A gate electrode is formed over the tapered portions and the channel region significantly increasing a surface of the gate electrode facing the source and drain regions. Therefore, known FET configurations having the dog-bone structure even have higher parasitic capacitances while showing detrimental electrostatic behaviors and high resistances, leading to problems when manufacturing semiconductor devices with high performance and low power consumption.
Another problem that is encountered in the fabrication of MOSFET integrated circuits as the device size shrinks is the correct placement of contacts, for example the contacts to the source and drains of individual transistors. As the pitch (the spacing from gate to gate) decreases below a certain dimension, it is important to have a self-aligning method for positioning the contacts. In order to reduce series resistance, it is also important to form silicided contacts to the source and drain regions. Metal silicides must not be subjected to high temperatures, so the silicided contacts, including self-aligned silicided contacts, must be formed after most of the high temperature processing steps.
Accordingly, it is desirable to provide methods for fabricating integrated circuits that include FinFETs having improved dynamical and electrical properties. It is also desirable to provide methods for fabricating integrated circuits with self-aligned contacts. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
Accordingly, it is an object to provide FinFETs having improved dynamical behavior and showing improved electrical properties while enabling high performance and improved power characteristics at further reduced dimension nodes.